Implementación de filtros digitales en FPGA

Abstract

Abstract: In this work, the design and implementation of FIR and IIR digital filters in VHDL for FPGAs is presented, where the different implemented structures are analyzed taking into account parameters such as data lengths, precision and filter order. The coefficients for the FIR and IIR filters have been calculated using the constant ripple and elliptic filter methods, respectively, through the Octave software. In addition, the algorithms implemented in Octave served to perform the fixed point to floating point conversion of the calculated coefficients, as well as to the binary conversion for processing by the FPGA. The testbench implemented for reading the filter data results in VHDL allowed to analyze and compare them with the results obtained in Octave. Finally, the Vivado synthesis tool was used for the VHDL design of the three FIR and IIR structures, with both behavioral and structural architectures.